1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to methods for forming multilevel interconnect structures that include dielectric materials having low dielectric constants.
2. Description of the Related Art
Integrated circuit geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices on a chip doubles every two years. Today's fabrication facilities are routinely producing devices having 0.1 μm feature sizes, and tomorrow's facilities soon will be producing devices having even smaller feature sizes.
The continued reduction in device geometries has generated a demand for films having low dielectric constant (k) values because the capacitive coupling between adjacent metal lines must be reduced to further reduce the size of devices on integrated circuits. For example, the scaling of CMOS (complementary field-effect transistor) device requires a continuous reduction to the RC (resistive capacitive) delay in the BEOL (Back-End-Of-the-Line) interconnects. To meet this requirement the dielectric constant (k) of the insulating layers used in the BEOL must be further reduced.
Over the last 10-15 years, the semiconductor industry went through many cycles in reducing the dielectric constant of the insulating layers, from using pure silicon dioxide (SiO2) with k=4.2 to the present day of porous carbon doped silicon oxide film, which comprises silicon, carbon, oxygen and hydrogen (commonly referred as SiCOH), with k=2.4. Conventional techniques generally use two methods to reduce k: (1) adding carbon to the SiO2 matrix and (2) adding porosity. However, these methods of reducing k result in lower mechanical properties compared to that of SiO2. These low mechanical properties, such as low modulus, and low hardness, made it difficult to integrate such films with metal lines, for example copper lines, in the dual damascene flow, which is generally used in forming BEOL interconnects. Additionally, future technologies (32 nm node and beyond) will require higher porosity in the SiCOH films. However, the loss of mechanical properties with higher porosity would indicate a lower limit of k˜2.0 for this type of films.
Therefore, in view of the continuing decrease in integrated circuit feature sizes and existing problems in the conventional methods, there remains a need for a method of forming dielectric layers having dielectric constants lower than 2.0